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MERC to conduct hearing on Mumbai power outage next week

Mumbai, Oct 18 : The Maharashtra Electricity Regulatory Commission (MERC) on Saturday said it will be making a suo motu hearing on the Mumbai power outage next week.

A rare citywide power outage paralysed Mumbai on October 12, halting suburban train services, trapping people in lifts and disrupting work-from-home adopted by millions during the ongoing pandemic.

The regulatory body will be undertaking a e-hearing regarding the incident on October 21 at 1030 hrs, MERC said in a notice.

The Commission said it has received a preliminary report about the grid failure from the Maharashtra State Load Dispatch Center (MSLDC) explaining the antecedent conditions , sequence of events , affected load and status of recovery of the system etc.

In the report, MSLDC has stated that the detailed report will be submitted after thorough analysis of the occurrence and collection of exact data from all the stakeholders, MERC said, asking the Center to submit the same by Monday evening.

It has also got preliminary reports from Tata Power Company – Generation, and Adani Electricity Mumbai – Distribution, but other transmission licensees, distribution licensees and users have not submitted the details.

At the hearing, it will discuss reasons for the occurrence of the outage, if standard protocol was followed to restore the grid and reasons for delay in restoring, response of all the stakeholders, if the islanding system operated as envisaged, priority accorded while restoring and also ways to prevent a reoccurrence of the same, as per the notice.

The notice was sent to state-run electricity distribution and transmission companies, Tata Power, Adani Electricity Mumbai, BEST and railways officials.

At present, state-run MSETCL and private sector Tata Power are in a blame game over what led to the major power outage which took over 14 hours to resolve.

MSETCL says the islanding system could not be triggered because Tata’s generation started very late, while Tata blames a cascading tripping of circuits for the fault.

SourcePTI

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